Towards Protocol Accelerator hardware (for “R2D2 and C-3PO world”)

General
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Inspired by @kylemathews post What technologies will usher in an Age of Protocols?

I had a thought. What would a “protocol accelerator” chip look like? Low-level hardware designed as a foundation for extreme protocol-aware tech? An accelerator chip, or a chiplet or a board?

Some possible features:

  1. Zero-knowledge ops
  2. Encryption computations
  3. Support for all low-level comms protocols (wifi, bluetooth, rfid, nfc, cellular…)
  4. SDR (software-defined radio)
  5. Deep archival distributed memory models (IPFS etc)
  6. And of course optimize for running blockchain light/heavy nodes

Meta question: All features could benefit from AI, so how much of “protocol acceleration” should be AI acceleration?

IoT hardware already goes after a lot of these. In many cases, “protocolizing” hardware is about adding a protocol to existing hardware. For eg: Arduino+WiFi = ESP32. But I’m thinking more generally, what it means to design protocol-forward or protocol-positive hardware at the lowest level? And can you design hardware to go up the stack to accelerate/benefit protocols at higher levels of abstraction (tcp/ip, ssh, http, rest,… all the way to AI and even human protocols).

One vision question: What chipsets would R2D2 and C-3PO from Star Wars run? Remember: R2D2 can plug into and hack any sort of electronics infrastructure while C-3PO can speak billions of languages and presumably handle the corresponding cultural protocols like handshakes, diplomatic niceties, and rituals.

Why is this interesting? Because enabling protocol-aware technology design at the lowest-possible level of abstraction creates the maximum possible leverage higher up the stack.

It’s no accident btw that the vision targets are 2 fictional robots. I think AI+protocols = robots to first order. Or to put it another way, protocols are how you get to embodiment for AI.

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We spent a little bit of time looking at content addressable routing, at the network layer. There’s probably something there.

I think SDR is directionally correct, but then, other than a secure enclave, unclear which of the rest you need. Basically, what can one do in sufficiently capable software?

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I’m reminded of this talk by Jim Keller

The key point is that graphs can serve as a common language or protocol between AI software models and specialized hardware architectures. By aligning the mathematical primitives in hardware (arrays, matrices, etc.) with the graph operations used in AI frameworks, we can achieve better performance and efficiency.

This, I think, aligns with “protocol-aware hardware design”. In this case, the protocol is the mathematical language of graphs that bridges software and hardware. By optimizing hardware to natively support graph primitives, we are essentially “accelerating” the protocol that AI models use.

AI Models are Graphs
AI Models are Graphs1536×855 154 KB

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Jim is a long-term client of mine, and at some point I’m hoping to protocol-pill him

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RISC-V is the biggest thing happening in protocols X hardware right now.

We saw the proprietary IP stack happen in Web 1.0 in building core internet routers, backplanes, and a bunch of other pieces – with protocols all in software, and the money all happening in the hardware / proprietary SW of the devices.

Oxide Computer’s Moore’s Scofflaws is great Moore's Scofflaws / Oxide – and also reaches back to those web 1.0 days.

Solaris licensing costs $$$ for all the new startups back then!

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